Within the European project JRA-12, we have designed a general purpose PreAmplifier-DIscriminator (PADI) ASIC to be used as Front-End-Electronics (FEE) for the readout of timing Resistive-Plate Chambers (RPC) in the CBM experiment at FAIR. These fast timing detectors deliver signals with rise times tR<500 ps and generate a prompt charge usually in the range of 30 to 2000 fC. Time resolution of Â¿tD<50 ps can be reached provided the preamplifier-discriminator stage has an intrinsic electronic resolution of Â¿tE <15 ps. The first prototype developed was PADI-1, a three-channel ASIC in 0.18 Â¿m CMOS technology. The subsequent versions PADI-2 to -4 have been changed from voltage to current biasing, which leads to an increase of the crosstalk rejection ratio at chip level, of more then 20 dB. PADI-2 and PADI-3 have different LVDS output levels, since they will be connected to a High Resolution TDC chip for digitization which is currently under development (GET4) requiring LVDS input signals. On all chips the number of channels has been increased to four and an OR feature allows to daisy-chain chips for trigger purpose. PADI-4 finally was developed for diamond timing detectors. In this article we present the results of comparative measurements with all these prototypes and define the ideas and goals for a next iteration.